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Data Sheet

ADV7340/ADV7341

Rev. C | Page 29 of 108

MPU PORT DESCRIPTION

Devices such as a microprocessor can communicate with the

ADV7340/ADV7341 through a 2-wire serial (I2C-compatible)

bus. After power-up or reset, the MPU port is configured for

I2C operation.

I2C OPERATION

The ADV7340/ADV7341 support a 2-wire serial (I2C-compatible)

microprocessor bus driving multiple peripherals. This port

operates in an open-drain configuration. Two wires, serial data

(SDA) and serial clock (SCL), carry information between any

device connected to the bus and the ADV7340/ADV7341. The

slave address of the device depends on the device (ADV7340 or

ADV7341), the operation (read or write), and the state of the

ALSB pin (0 or 1). See Table 16, Figure 47, and Figure 48. The

LSB sets either a read or a write operation. Logic 1 corresponds to

a read operation, and Logic 0 corresponds to a write operation.

A1 is controlled by setting the ALSB pin of the ADV7340/

ADV7341 to Logic 0 or Logic 1.

Table 16. ADV7340/ADV7341 I2C Slave Addresses

Device

ALSB

Operation

Slave Address

ADV7340

Write

0xD4

Read

0xD5

Write

0xD6

Read

0xD7

ADV7341

Write

0x54

Read

0x55

Write

0x56

Read

0x57

Figure 47. ADV7340 I2C Slave Address

Figure 48. ADV7341 I2C Slave Address

Analog Devices, Inc., strongly recommends tying ALSB to

VDD_IO. If this is not done, a power supply sequence (PSS) may be

required. For more information on the PSS, see the Power Supply

Sequencing section. The various devices on the bus use the

following protocol. The master initiates a data transfer by

establishing a start condition, defined by a high-to-low

transition on SDA while SCL remains high. This indicates that

an address/data stream follows. All peripherals respond to the

start condition and shift the next eight bits (7-bit address plus

the R/W bit). The bits are transferred from MSB down to LSB.

The peripheral that recognizes the transmitted address responds

by pulling the data line low during the ninth clock pulse. This is

known as an acknowledge bit. All other devices withdraw from

the bus at this point and maintain an idle condition. The idle

condition occurs when the device monitors the SDA and SCL

lines waiting for the start condition and the correct transmitted

address. The R/W bit determines the direction of the data.

Logic 0 on the LSB of the first byte means that the master writes

information to the peripheral. Logic 1 on the LSB of the first byte

means that the master reads information from the peripheral.

The ADV7340/ADV7341 act as a standard slave device on the

bus. The data on the SDA pin is eight bits long, supporting the

7-bit addresses plus the R/W bit. It interprets the first byte as

the device address and the second byte as the starting subaddress.

There is a subaddress auto-increment facility. This allows data

to be written to or read from registers in ascending subaddress

sequence starting at any valid subaddress. A data transfer is

always terminated by a stop condition. The user can also access

any unique subaddress register on a one-by-one basis without

updating all the registers.

Stop and start conditions can be detected at any stage during the

data transfer. If these conditions are asserted out of sequence

with normal read and write operations, they cause an immediate

jump to the idle condition. During a given SCL high period, the

user should issue only a start condition, a stop condition, or a

stop condition followed by a start condition. If an invalid sub-

address is issued by the user, the ADV7340/ADV7341 do not

issue an acknowledge but return to the idle condition. If the user

uses the auto-increment method of addressing the encoder and

exceeds the highest subaddress, the following actions are taken:

•

In read mode, the highest subaddress register contents are

output until the master device issues a no acknowledge. This

indicates the end of a read. A no acknowledge condition

occurs when the SDA line is not pulled low on the ninth pulse.

•

In write mode, the data for the invalid byte is not loaded

into any subaddress register, a no acknowledge is issued by

the ADV7340/ADV7341, and the parts return to the idle

condition.

Figure 49 shows a data transfer for a write sequence and the start

and stop conditions. Figure 50 shows bus write and read

sequences.

ADDRESS

CONTROL

SET UP BY

ALSB

READ/WRITE

CONTROL

WRITE

READ

READ/WRITE

CONTROL

WRITE

READ

ADDRESS

CONTROL

SET UP BY

ALSB

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