ADV7341_15 datasheet(75/108 Pages) AD

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Data Sheet

ADV7340/ADV7341

Rev. C | Page 75 of 108

External filter and buffer components connected to the DAC

outputs should be placed as close as possible to the ADV7340/

ADV7341 to minimize the possibility of noise pickup from

neighboring circuitry and to minimize the effect of trace

capacitance on output bandwidth. This is particularly important

when operating in low-drive mode (RSETx = 4.12 kΩ, RL = 300 Ω).

Power Supplies

It is recommended that a separate regulated supply be provided

for each power domain (VAA, VDD, VDD_IO, and PVDD). For

optimal performance, linear regulators rather than switch mode

regulators should be used. If switch mode regulators must be

used, care must be taken with regard to the quality of the output

voltage in terms of ripple and noise. This is particularly true for

the VAA and PVDD power domains. Each power supply should be

individually connected to the system power supply at a single

point through a suitable filtering device, such as a ferrite bead.

Power Supply Decoupling

It is recommended that each power supply pin be decoupled

with 10 nF and 0.1 µF ceramic capacitors. The VAA, PVDD,

VDD_IO, and both VDD pins should be individually decoupled to

ground. The decoupling capacitors should be placed as close as

possible to the ADV7340/ADV7341 with the capacitor leads

kept as short as possible to minimize lead inductance.

A 1 µF tantalum capacitor is recommended across the VAA

supply in addition to the 10 nF and 0.1 µF ceramic capacitors.

Power Supply Sequencing

If the ALSB pin is tied low, a power supply sequence is required for

proper operation of the part. The VDD_IO power supply must be

established a minimum of 250 µs prior to the VDD power supply

being established. The VAA and PVDD power supplies can be

established at any time and in any order. Tying ALSB to VDD_IO

completely removes this PSS requirement.

Digital Signal Interconnect

The digital signal traces should be isolated as much as possible

from the analog outputs and other analog circuitry. Digital

signal traces should not overlay the VAA or PVDD power planes.

Due to the high clock rates used, avoid long clock traces to the

ADV7340/ADV7341 to minimize noise pickup.

Any pull-up termination resistors for the digital inputs should

be connected to the VDD_IO power supply.

Any unused digital inputs should be tied to ground.

Analog Signal Interconnect

DAC output traces should be treated as transmission lines with

appropriate measures taken to ensure optimal performance (for

example, impedance matched traces). The DAC output traces

should be kept as short as possible. The termination resistors on

the DAC output traces should be placed as close as possible to,

and on the same side of the PCB as, the ADV7340/ADV7341.

To avoid crosstalk between the DAC outputs, it is recom-

mended that as much space as possible be left between the

traces connected to the DAC output pins. Adding ground traces

between the DAC output traces is also recommended.

ADV7341 数据表(PDF) 75 Page - Analog Devices

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