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ADV7340/ADV7341

Data Sheet

Rev. C | Page 54 of 108

DESIGN FEATURES

OUTPUT OVERSAMPLING

The ADV7340/ADV7341 include two on-chip phase-locked

loops (PLLs) that allow for oversampling of SD, ED, and HD

video data. Table 41 shows the various oversampling rates

supported in the ADV7340/ADV7341.

SD Only, ED Only, and HD Only Modes

PLL 1 is used in SD only, ED only, and HD only modes. PLL 2 is

unused in these modes. PLL 1 is disabled by default and can be

enabled using Subaddress 0x00, Bit 1 = 0.

SD and ED/HD Simultaneous Modes

Both PLL 1 and PLL 2 are used in simultaneous modes. The use

of two PLLs allows for independent oversampling of SD and

ED/HD video. PLL 1 is used to oversample SD video data, and

PLL 2 is used to oversample ED/HD video data. In simultaneous

modes, PLL 2 is always enabled. PLL 1 is disabled by default and

can be enabled using Subaddress 0x00, Bit 1 = 0.

External Sync Polarity

For SD and ED/HD modes, the ADV7340/ADV7341 typically

expect HS and VS to be low during their respective blanking

periods. When the CEA861 compliance bit (Subaddress 0x39,

Bit 5 for ED/HD modes and Subaddress 0x86, Bit 3 for SD

modes) is enabled, however, the part expects the HS or VS to be

active low or high depending on the input format selected

(Subaddress 0x30, Bits [7:3]).

If a different polarity other than the default is needed for

ED/HD modes, Subaddress 0x3A, Bits [2:0] can be used to

individually invert P_HSYNC, P_VSYNC, or P_BLANK

regardless of whether or not CEA-861-B mode is enabled. It is

not possible to invert S_HSYNC or S_VSYNC.

HD INTERLACE EXTERNAL P_HSYNC AND

P_VSYNC CONSIDERATIONS

If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 01

or higher, the user should set Subaddress 0x02, Bit 1 to high to

ensure exactly correct timing in HD interlace modes when

using the P_HSYNC and P_VSYNC synchronization signals. If

this bit is set to low, the first active pixel on each line is masked.

Also, Pr and Pb outputs are swapped when using the YCrCb

4:2:2 input format. Setting Subaddress 0x02, Bit 1 to low causes

the encoder to behave in the same way as the first version of

silicon (that is, this setting is backward compatible).

If the encoder revision code (Subaddress 0xBB, Bits[7:6]) = 00,

the setting of Subaddress 0x02, Bit 1 has no effect. In this

version of the encoder, the first active pixel is masked. Also, Pr

and Pb outputs are swapped when using the YCrCb 4:2:2 input

format. To avoid these limitations, use the newer revision of

silicon or use a different type of synchronization.

These considerations apply only to the HD interlace modes

with external P_HSYNC and P_VSYNC synchronization

(EAV/SAV mode is not affected and always has exactly correct

timing). There is no negative effect in setting Subaddress 0x02,

Bit 0 to high, and this bit can remain high for all the other video

standards.

Table 41. Output Oversampling Modes and Rates

Input Mode Subaddress 0x01 Bits[6:4]

PLL and Oversampling Control

Subaddress 0x00, Bit 1

Oversampling Mode and Rate

000

SD only

SD (2×)

000

SD only

SD (16×)

001/010

ED only

ED (1×)

001/010

ED only

ED (8×)

001/010

HD only

HD (1×)

001/010

HD only

HD (4×)

011/100

SD and ED

SD (2×) and ED (8×)

011/100

SD and ED

SD (16×) and ED (8×)

011/100

SD and HD

SD (2×) and HD (4×)

011/100

SD and HD

SD (16×) and HD (4×)

111

ED only (at 54 MHz)

ED only (at 54 MHz) (1×)

111

ED only (at 54 MHz)

ED only (at 54 MHz) (8×)

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