 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADV7341 数据表(PDF) 18 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADV7341 数据表(HTML) 18 Page - Analog Devices |
|
|
18 / 108 page  ADV7340/ADV7341 Data Sheet Rev. C | Page 18 of 108 Figure 15. ED-DDR, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Input Timing Diagram Y9 TO Y2/ Y9 TO Y0 Cb0 Y0 Cr0 Y1 b a a = 32 CLKCYCLES FOR 525p a = 24 CLKCYCLES FOR 625p AS RECOMMENDED BY STANDARD b(MIN) = 244 CLKCYCLES FOR 525p b(MIN) = 264 CLKCYCLES FOR 625p P_HSYNC P_VSYNC P_BLANK c Y OUTPUT c = PIPELINE DELAY. PLEASE REFER TO RELEVANT PIPELINE DELAY. THIS CAN BE FOUND IN THE DIGITAL TIMING SPECIFICATION SECTION OF THE DATA SHEET. A FALLING EDGE OF HSYNC INTO THE ENCODER GENERATES A SYNC FALLING EDGE ON THE OUTPUT AFTER A TIME EQUAL TO THE PIPELINE DELAY. |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
