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ADV7341 数据表(PDF) 100 Page - Analog Devices |
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ADV7341 数据表(HTML) 100 Page - Analog Devices |
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100 / 108 page  ADV7340/ADV7341 Data Sheet Rev. C | Page 100 of 108 ENHANCED DEFINITION Table 85. ED Configuration Scripts Input Format Input Data Width1 Synchronization Format Input Color Space Output Color Space Table Number 525p at 59.94 Hz 10-bit DDR EAV/SAV YCrCb YPrPb Table 86 525p at 59.94 Hz 10-bit DDR HSYNC/VSYNC YCrCb YPrPb Table 87 525p at 59.94 Hz 10-bit DDR EAV/SAV YCrCb RGB Table 88 525p at 59.94 Hz 10-bit DDR HSYNC/VSYNC YCrCb RGB Table 89 525p at 59.94 Hz 20-bit SDR EAV/SAV YCrCb YPrPb Table 90 525p at 59.94 Hz 20-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 91 525p at 59.94 Hz 20-bit SDR EAV/SAV YCrCb RGB Table 92 525p at 59.94 Hz 20-bit SDR HSYNC/VSYNC YCrCb RGB Table 93 525p at 59.94 Hz 30-bit SDR EAV/SAV YCrCb YPrPb Table 94 525p at 59.94 Hz 30-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 95 525p at 59.94 Hz 30-bit SDR EAV/SAV YCrCb RGB Table 96 525p at 59.94 Hz 30-bit SDR HSYNC/VSYNC YCrCb RGB Table 97 525p at 59.94 Hz 30-bit SDR HSYNC/VSYNC RGB RGB Table 98 625p at 50 Hz 10-bit DDR EAV/SAV YCrCb YPrPb Table 99 625p at 50 Hz 10-bit DDR HSYNC/VSYNC YCrCb YPrPb Table 100 625p at 50 Hz 10-bit DDR EAV/SAV YCrCb RGB Table 101 625p at 50 Hz 10-bit DDR HSYNC/VSYNC YCrCb RGB Table 102 625p at 50 Hz 20-bit SDR EAV/SAV YCrCb YPrPb Table 103 625p at 50 Hz 20-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 104 625p at 50 Hz 20-bit SDR EAV/SAV YCrCb RGB Table 105 625p at 50 Hz 20-bit SDR HSYNC/VSYNC YCrCb RGB Table 106 625p at 50 Hz 30-bit SDR EAV/SAV YCrCb YPrPb Table 107 625p at 50 Hz 30-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 108 625p at 50 Hz 30-bit SDR EAV/SAV YCrCb RGB Table 109 625p at 50 Hz 30-bit SDR HSYNC/VSYNC YCrCb RGB Table 110 625p at 50 Hz 30-bit SDR HSYNC/VSYNC RGB RGB Table 111 1 SDR = single data rate. DDR = dual data rate. Table 86. 10-Bit 525p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x04 525p at 59.94 Hz. EAV/SAV synchro- nization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 87. 10-Bit 525p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. |
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