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ADV7341 数据表(PDF) 104 Page - Analog Devices |
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ADV7341 数据表(HTML) 104 Page - Analog Devices |
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104 / 108 page  ADV7340/ADV7341 Data Sheet Rev. C | Page 104 of 108 HIGH DEFINITION Table 112. HD Configuration Scripts Input Format Input Data Width1 Synchronization Format Input Color Space Output Color Space Table Number 720p at 60 Hz/59.94 Hz 10-bit DDR EAV/SAV YCrCb YPrPb Table 113 720p at 60 Hz/59.94 Hz 10-bit DDR HSYNC/VSYNC YCrCb YPrPb Table 114 720p at 60 Hz/59.94 Hz 10-bit DDR EAV/SAV YCrCb RGB Table 115 720p at 60 Hz/59.94 Hz 10-bit DDR HSYNC/VSYNC YCrCb RGB Table 116 720p at 60 Hz/59.94 Hz 20-bit SDR EAV/SAV YCrCb YPrPb Table 117 720p at 60 Hz/59.94 Hz 20-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 118 720p at 60 Hz/59.94 Hz 20-bit SDR EAV/SAV YCrCb RGB Table 119 720p at 60 Hz/59.94 Hz 20-bit SDR HSYNC/VSYNC YCrCb RGB Table 120 720p at 60 Hz/59.94 Hz 30-bit SDR EAV/SAV YCrCb YPrPb Table 121 720p at 60 Hz/59.94 Hz 30-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 122 720p at 60 Hz/59.94 Hz 30-bit SDR EAV/SAV YCrCb RGB Table 123 720p at 60 Hz/59.94 Hz 30-bit SDR HSYNC/VSYNC YCrCb RGB Table 124 720p at 60 Hz/59.94 Hz 30-bit SDR HSYNC/VSYNC RGB RGB Table 125 1080i at 30 Hz/29.97 Hz 10-bit DDR EAV/SAV YCrCb YPrPb Table 126 1080i at 30 Hz/29.97 Hz 10-bit DDR HSYNC/VSYNC YCrCb YPrPb Table 127 1080i at 30 Hz/29.97 Hz 10-bit DDR EAV/SAV YCrCb RGB Table 128 1080i at 30 Hz/29.97 Hz 10-bit DDR HSYNC/VSYNC YCrCb RGB Table 129 1080i at 30 Hz/29.97 Hz 20-bit SDR EAV/SAV YCrCb YPrPb Table 130 1080i at 30 Hz/29.97 Hz 20-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 131 1080i at 30 Hz/29.97 Hz 20-bit SDR EAV/SAV YCrCb RGB Table 132 1080i at 30 Hz/29.97 Hz 20-bit SDR HSYNC/VSYNC YCrCb RGB Table 133 1080i at 30 Hz/29.97 Hz 30-bit SDR EAV/SAV YCrCb YPrPb Table 134 1080i at 30 Hz/29.97 Hz 30-bit SDR HSYNC/VSYNC YCrCb YPrPb Table 135 1080i at 30 Hz/29.97 Hz 30-bit SDR EAV/SAV YCrCb RGB Table 136 1080i at 30 Hz/29.97 Hz 30-bit SDR HSYNC/VSYNC YCrCb RGB Table 137 1080i at 30 Hz/29.97 Hz 30-bit SDR HSYNC/VSYNC RGB RGB Table 138 1 SDR = single data rate. DDR = dual data rate. Table 113. 10-Bit 720p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x2C 720p at 60 Hz/59.94 Hz. EAV/SAV syn- chronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. 0x33 0x6C 10-bit input enabled. Table 114. 10-Bit 720p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (4×). 0x01 0x20 HD-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x28 720p at 60 Hz/59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.3 output levels. 0x31 0x01 Pixel data valid. 4× oversampling. 0x33 0x6C 10-bit input enabled. |
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