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ADV7341 数据表(PDF) 101 Page - Analog Devices |
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ADV7341 数据表(HTML) 101 Page - Analog Devices |
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101 / 108 page  Data Sheet ADV7340/ADV7341 Rev. C | Page 101 of 108 Table 88. 10-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x04 525p at 59.94 Hz. EAV/SAV synchro- nization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 89. 10-Bit 525p YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 90. 20-Bit 525p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x04 525p at 59.94 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled (10 × 2 = 20-bit). Table 91. 20-Bit 525p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled (10 × 2 = 20-bit). Table 92. 20-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x04 525p at 59.94 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled (10 × 2 = 20-bit). Table 93. 20-Bit 525p YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled (10 × 2 = 20-bit). Table 94. 30-Bit 525p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x04 525p at 59.94 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x2C 4:4:4 input data. 10-bit input enabled (10 × 3 = 30-bit). Table 95. 30-Bit 525p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x2C 4:4:4 input data. 10-bit input enabled (10 × 3 = 30-bit). |
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