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ADV7341 数据表(PDF) 102 Page - Analog Devices |
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ADV7341 数据表(HTML) 102 Page - Analog Devices |
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102 / 108 page  ADV7340/ADV7341 Data Sheet Rev. C | Page 102 of 108 Table 96. 30-Bit 525p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x04 525p at 59.94 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x2C 4:4:4 input data. 10-bit input enabled (10 × 3 = 30-bit). Table 97. 30-Bit 525p YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x2C 4:4:4 input data. 10-bit input enabled (10 × 3 = 30-bit). Table 98. 30-Bit 525p RGB In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x00 525p at 59.94 Hz. HSYNC/VSYNC synch- ronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x2C 4:4:4 input data. 10-bit input enabled (10 × 3 = 30-bit). 0x35 0x02 RGB input enabled. Table 99. 10-Bit 625p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x1C 625p at 50 Hz. EAV/SAV synchroniza- tion. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 100. 10-Bit 625p YCrCb In, YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x30 0x18 625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 101. 10-Bit 625p YCrCb In (EAV/SAV), RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x1C 625p at 50 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 102. 10-Bit 625p YCrCb In, RGB Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x20 ED-DDR input mode. Luma data clocked on falling edge of CLKIN. 0x02 0x10 RGB output enabled. RGB output sync enabled. 0x30 0x18 625p at 50 Hz. HSYNC/VSYNC synchronization. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled. Table 103. 20-Bit 625p YCrCb In (EAV/SAV), YPrPb Out Subaddress Setting Description 0x17 0x02 Software reset. 0x00 0x1C All DACs enabled. PLL enabled (8×). 0x01 0x10 ED-SDR input mode. 0x30 0x1C 625p at 50 Hz. EAV/SAV synchroni- zation. EIA-770.2 output levels. 0x31 0x01 Pixel data valid. 0x33 0x6C 10-bit input enabled (10 × 2 = 20-bit). |
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