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ADV7341 数据表(PDF) 15 Page - Analog Devices |
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ADV7341 数据表(HTML) 15 Page - Analog Devices |
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15 / 108 page  Data Sheet ADV7340/ADV7341 Rev. C | Page 15 of 108 Figure 7. ED/HD-SDR Only, 24-/30-Bit, 4:4:4 RGB Pixel Input Mode (Input Mode 001) Figure 8. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb (HSYNC/VSYNC) Pixel Input Mode (Input Mode 010) Figure 9. ED/HD-DDR Only, 8-/10-Bit, 4:2:2 YCrCb (EAV/SAV) Pixel Input Mode (Input Mode 010) CLKIN_A C9 TO C2/ C9 TO C0 G0 G1 G2 G3 G4 G5 B0 B1 B2 B3 B4 B5 R0 R1 R2 R3 R4 R5 Y9 TO Y2/ Y9 TO Y0 CONTROL OUTPUTS S9 TO S2/ S9 TO S0 P_HSYNC, P_VSYNC, CONTROL INPUTS P_BLANK t9 t10 t12 t11 t14 t13 CLKIN_A* Y9 TO Y2/ Y9 TO Y0 *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. CONTROL OUTPUTS Cr2 Y2 Cb2 Y1 Cr0 Y0 Cb0 t9 t10 t12 t11 t12 t11 t14 t13 P_HSYNC, P_VSYNC, CONTROL INPUTS P_BLANK Y1 Cr0 Y0 Cb0 XY 00 00 3FF *LUMA/CHROMA CLOCK RELATIONSHIP CAN BE INVERTED USING SUBADDRESS 0x01, BITS 1 AND 2. CLKIN_A* Y9 TO Y2/ Y9 TO Y0 CONTROL OUTPUTS t9 t10 t12 t11 t12 t11 t14 t13 |
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