ADV7341_15 datasheet(22/108 Pages) AD

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ADV7340/ADV7341

Data Sheet

Rev. C | Page 22 of 108

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 20. Pin Configuration

Table 15. Pin Function Descriptions

Pin No.

Mnemonic

Input/

Output

Description

13, 12,

9 to 2

Y9 to Y0

10-Bit Pixel Port (Y9 to Y0). Y0 is the LSB. Refer to Table 36 for input modes.

29 to 25,

18 to 14

C9 to C0

10-Bit Pixel Port (C9 to C0). C0 is the LSB. Refer to Table 36 for input modes.

62 to 58,

55 to 51

S9 to S0

10-Bit Pixel Port (S9 to S0). S0 is the LSB. Refer to Table 36 for input modes.

CLKIN_A

Pixel Clock Input for HD Only (74.25 MHz), ED1 Only (27 MHz or 54 MHz), or SD Only (27 MHz).

CLKIN_B

Pixel Clock Input for Dual Modes Only. Requires a 27 MHz reference clock for ED operation or a

74.25 MHz reference clock for HD operation.

S_HSYNC

I/O

SD Horizontal Synchronization Signal. This pin can also be configured to output an SD, ED, or HD

horizontal synchronization signal. See the External Horizontal and Vertical Synchronization

Control section.

S_VSYNC

I/O

SD Vertical Synchronization Signal. This pin can also be configured to output an SD, ED, or HD

vertical synchronization signal. See the External Horizontal and Vertical Synchronization Control

section.

P_HSYNC

ED/HD Horizontal Synchronization Signal. See the External Horizontal and Vertical

Synchronization Control section.

P_VSYNC

ED/HD Vertical Synchronization Signal. See the External Horizontal and Vertical Synchronization

Control section.

P_BLANK

ED/HD Blanking Signal. See the External Horizontal and Vertical Synchronization Control section.

SFL

I/O

Subcarrier Frequency Lock (SFL) Input.

RSET1

This pin is used to control the amplitudes of the DAC 1, DAC 2, and DAC 3 outputs. For full-drive

operation (for example, into a 37.5 Ω load), a 510 Ω resistor must be connected from RSET1 to

AGND. For low-drive operation (for example, into a 300 Ω load), a 4.12 kΩ resistor must be

connected from RSET1 to AGND.

RSET2

This pin is used to control the amplitudes of the DAC 4, DAC 5, and DAC 6 outputs. A 4.12 kΩ

resistor must be connected from RSET2 to AGND.

64 63 62

60 59 58

57 56 55 54 53 52 51 50 49

RSET1

VREF

COMP1

DAC 3

DAC 2

DAC 1

SFL

VAA

AGND

DAC 4

DAC 6

RSET2

COMP2

PVDD

EXT_LF1

DAC 5

VDD_IO

VDD

DGND

17 18

21 22 23

24 25 26

27 28 29 30 31 32

PIN 1

ADV7340/ADV7341

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