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ADV7341 数据表(PDF) 107 Page - Analog Devices

部件名 ADV7341
功能描述  Multiformat Video Encoder, Six 12-Bit Noise Shaped Video DACS
PDF  108 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  AD [Analog Devices]
网页  http://www.analog.com
标志 AD - Analog Devices

ADV7341 数据表(HTML) 107 Page - Analog Devices

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Data Sheet
ADV7340/ADV7341
Rev. C | Page 107 of 108
Table 131. 20-Bit 1080i YCrCb In, YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x68
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled (10 × 2 = 20-bit).
Table 132. 20-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled (10 × 2 = 20-bit).
Table 133. 20-Bit 1080i YCrCb In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x68
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x6C
10-bit input enabled (10 × 2 = 20-bit).
Table 134. 30-Bit 1080i YCrCb In (EAV/SAV), YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x2C
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Table 135. 30-Bit 1080i YCrCb In, YPrPb Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x30
0x68
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x2C
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Table 136. 30-Bit 1080i YCrCb In (EAV/SAV), RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x6C
1080i at 30 Hz/29.97 Hz. EAV/SAV syn-
chronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x2C
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Table 137. 30-Bit 1080i YCrCb In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x68
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x2C
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
Table 138. 30-Bit 1080i RGB In, RGB Out
Subaddress
Setting
Description
0x17
0x02
Software reset.
0x00
0x1C
All DACs enabled. PLL enabled (4×).
0x01
0x10
HD-SDR input mode.
0x02
0x10
RGB output enabled. RGB output sync
enabled.
0x30
0x68
1080i at 30 Hz/29.97 Hz. HSYNC/VSYNC
synchronization. EIA-770.3 output levels.
0x31
0x01
Pixel data valid. 4× oversampling.
0x33
0x2C
4:4:4 input data. 10-bit input enabled
(10 × 3 = 30-bit).
0x35
0x02
RGB input enabled.



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