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RM0352 数据表(PDF) 66 Page - STMicroelectronics |
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RM0352 数据表(HTML) 66 Page - STMicroelectronics |
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66 / 138 page  ARM© dual timer module (SP804) RM0352 66/138 DocID024647 Rev 1 PrimeCell ID2 register, TimerPCellID2 The TimerPCellID2 register is hard-coded and the fields in the register determine the reset value. Table 63 shows the bit assignment of the TimerPCellID2 register. PrimeCell ID3 register, TimerPCellID3 The TimerPCellID3 register is hard-coded and the fields in the register determine the reset value. Table 64 shows the bit assignment of the TimerPCellID3 register. Table 63. PrimeCell ID2 register bit assignments Bit Name Description [31:8] - RESERVED, read undefined, must be written as zeros [7:0] TimerPCellID2 These bits read back as 0x05 Table 64. PrimeCell ID3 register bit assignments Bit Name Description [31:8] - RESERVED, read undefined, must be written as zeros [7:0] TimerPCellID3 These bits read back as 0xB1 |
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