RM0352 datasheet(77/138 Pages) STMICROELECTRONICS

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RM0352

I2C bus interface

137

10.2.2

I2C slave control register (I2C_SCR)

Table 72. I2C slave control register (I2C_SCR)

Address:

I2CBaseAddress + 0x04

Type:

R/W

Reset:

0x000F0055

Description:

C slave control register

10.2.3

I2C master control register (I2C_MCR)

Table 73. I2C master control register (I2C_MCR)

Address:

I2CBaseAddress + 0x0C

Type:

R/W

Reset:

0x00000000

I2C slave control register (I2C_SCR)

31 30 29 28 27 26

24 23 22 21 20 19

18 17 16 15

SLSU

RESERVED

ESA10

SA7

R/W

[31:16] SLSU: slave data setup time. SLSU defines the data setup time after SCL

clock stretching in terms of i2c_clk cycles. Data setup time is actually equal to

SLSU-1 clock cycles.

This value depends on the mode selected (standard/fast) and on i2c_clk

frequency. The needed setup time for the two modes are 250 ns and 100 ns

respectively. In the Brain device, the typical value for i2c_clk is 26.66 MHz. So

SLSU typical value should be 8 in standard mode and 4 in fast mode.

[9:7] ESA10: extended slave address 10-bit. ESA10 includes the extension (MSB

bits) to the SA7 register field in case of slave addressing mode set to 10-bit

(I2C_CR:SAM = 1)

[6:0] SA7: slave address 7-bit. SA7 includes the slave address 7-bit or the LSB bits

of the slave address 10-bit. The slave addressing mode is set according to the

I2C_CR:SAM setting.

I2C master control register (I2C_MCR)

29 28 27 26 25 24

23 22 21 20 19 18 17 16

RESERVED

LENGTH

EA10

R/W

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