RM0352 datasheet(27/138 Pages) STMICROELECTRONICS

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RM0352

Clock and reset management unit

137

5.4

CRMU registers

The CRMU registers are listed in

Table 7 on page 27 and are described in details in the

following pages.

The base address of the CRMU block in the Brain memory map is 0xAB00_0000.

Table 7. CRMU registers

Address

Name

Type Reset value

Description

CRMU_BASE + 0x00

CRMU_RESET_REASON

0x01

Indicates the cause of the last reset. See

Table 8: CRMU_REASON_RESET on

page 27.

CRMU_BASE + 0x04

CRMU_CCR0

0x1100

Clock and Reset Management Unit

Control register 0. See

Table 9:

CRMU_CCR0 on page 28.

CRMU_BASE + 0x08

CRMU_CCR1

0x00

Clock and Reset Management Unit

Control register 1 containing UART clock

divide factor. See

Table 13:

CRMU_CCR1 on page 29.

CRMU_BASE+ 0x0C

CRMU_CCR2

0x00000

Clock and Reset Management Unit

Control register 2. containing the

peripherals clock gating. See

Table 14:

CRMU_CCR2 on page 29.

CRMU_BASE+ 0x10

CRMU_ECCR0

0x00000000

Status register about ECC error

detection. See

Table 15: CRMU_ECCR0

on page 30

CRMU_BASE+ 0x14

CRMU_ECCR1

0x0

Control register for ECC RAM bank 0

management. See

Table 16:

CRMU_ECCR1 on page 30.

Table 8. CRMU_REASON_RESET

Address

Bit

Field name

Reset R/W

Description

CRMU_BASE + 0x0

REASON_POR

Reset caused by POR or by BOR

REASON_ECC

Reset caused by ECC

REASON_WDG

Reset caused by assertion of watchdog reset

REASON_SYSREQ

Reset caused by Cortex-M0 debug asserting

SYSRESETREQ

REASON_LOCKUP

Reset caused by Cortex-M0 asserting LOCKUP

signal

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