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RM0352 数据表(PDF) 31 Page - STMicroelectronics |
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RM0352 数据表(HTML) 31 Page - STMicroelectronics |
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31 / 138 page  DocID024647 Rev 1 31/138 RM0352 Embedded Flash memory 137 6 Embedded Flash memory 6.1 Description The Flash array consists of 64 kBytes or 16 kWords (16384 x 32-bit) and is outside the Flash wrapper. The Flash can be accessed per 32-bit for read access and per 16-bit for write access. Erasing the whole Flash will result in all ones in every bit cell of the Flash. Note: For any erase or write action on the Flash, the system clock must be configured to use an internal oscillator. The Flash is mapped on the AHB-Lite bus with the range described below: 6.2 Flash controller registers The Flash controller base address block in the Brain memory map is 0xA100_0000. Table 17. Flash memory section address Section Flash AHB start address Flash AHB end address Program memory with REMAP = ‘0’ 0x1001_0000 0x1001_FFFF Program memory with REMAP = ‘1’ 0x1002_0000 0x1002_FFFF |
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