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RM0352 数据表(PDF) 32 Page - STMicroelectronics

部件名 RM0352
功能描述  Brain smart hub family
PDF  138 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

RM0352 数据表(HTML) 32 Page - STMicroelectronics

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Embedded Flash memory
RM0352
32/138
DocID024647 Rev 1
6.3
Flash controller registers
6.3.1
Interrupt registers
The interrupt status, raw status and the mask register all have the same bit definition:
Table 18. Flash APB registers
Address
offset
Name
Width
RW
Reset
Description
0x00
COMMAND
8
RW
(1)
0x0000_0000
Commands for the module. See
Table 20: Flash
command register on page 34.
0x04
CONFIG
2
RW
(1)
0x0000_0049
Configure the wrapper. See
Table 21: Flash CONFIG
register on page 35.
0x08
IRQSTAT
5
RC
(2)
0x0000_0000
Flash status interrupts (masked). See
Table 19: Flash
interrupt register on page 32.
0x0C
IRQMASK
5
RW
(1)
0x0000_003F
Mask for interrupts. See
Table 19: Flash interrupt
register on page 32.
0x10
IRQRAW
5
RC
(2)
0x0000_0000
Status interrupts (unmasked). See
Table 19: Flash
interrupt register on page 32.
0x14
DATA
32
RW
(1)
0x0000_0000
Program cycle data. See
Section 6.3.2: Data register
on page 33.
0x18
ADDRESS
14
RW
(1)
0x0000_0000
Address for programming Flash, will auto-increment.
See
Section 6.3.3: Address register on page 33.
0x1C
UNLOCKM
32
RW
(1)
0xFFFF_FFFF
Unlock codeword (MSW): when test mode is active, the
Flash needs to be protected with an unlock code. See
Section 6.3.6: Unlock registers on page 36.
0x20
UNLOCKL
32
RW
(1)
0xFFFF_FFFF
Unlock codeword (LSW): when test mode is active, the
Flash needs to be protected with an unlock code. See
Section 6.3.6: Unlock registers on page 36.
0x24
LFSRVAL
32
RO
(3)
0xFFFF_FFFF
LFSR register needed for check after MASS READ
command. See
Section 6.3.7: LFSR register on
page 36
0x28 to
0x30
RESERVED
-
-
-
RESERVED
1.
RW = read and write.
2.
RC = read and write to clear.
3.
RO = read-only.
Table 19. Flash interrupt register
Bit
Name
Description
0
CMDDONE
Command is done.
1
CMDSTART
Command is started.
2
CMDERR
Command written while BUSY.
3
ILLCMD
Illegal command written.



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