RM0352 datasheet(39/138 Pages) STMICROELECTRONICS

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RM0352

Watchdog timer (WDG)

137

disabled the watchdog counter is also stopped, and when the interrupt is enabled the

counter will start from the programmed value, not the last count value.

Write access to the registers within the watchdog timer can be disabled by the use of the

watchdog lock register. Writing a value of 0x1ACC_E551 to this WDT_LOCK register allows

write access to all other registers; writing any other value disables write access. This feature

is included to allow some protection against software which might otherwise disable the

watchdog functionality.

7.2

WDG registers

The device communicates to the system via 32-bit-wide control registers accessible via the

AMBA™ rev. 2.0 “Advanced Peripheral Bus” (APB). These registers are listed in

Table 26

on page 39 and are described in details on the following pages.

The WDG base address is 0xAA00_0000.

Table 26. WDG register list

Address

Name

Description

WDG base + 0x000

WDT_LR

Watchdog load value register. See

Section 7.2.1:

Watchdog load register (WDT_LR) on page 41.

WDG base + 0x004

WDT_VAL

Watchdog current value (read-only) register. See

Section 7.2.2: Watchdog value register WDT_VAL on

page 41.

WDG base + 0x008

WDT_CR

Watchdog control register. See

Section 7.2.3:

Watchdog control register WDT_CR on page 42.

WDG base + 0x00C

WDT_ICR

Watchdog interrupt clear register. See

Section 7.2.4:

Watchdog interrupt clear register WDT_ICR on

page 42.

WDG base + 0x010

WDT_RIS

Watchdog raw interrupt status register. See

Section 7.2.5: Watchdog raw interrupt status register

WDT_RIS on page 43.

WDG base + 0x014

WDT_MIS

Watchdog masked interrupt status register. See

Section 7.2.6: Watchdog masked interrupt status

WDG base + 0x01C to 0xBFC

RESERVED

WDG base + 0xC00

WDT_LOCK

Watchdog lock register. See

Section 7.2.7: Watchdog

lock register WDT_LOCK on page 44.

WDG base + 0xC04 to 0xFDC

RESERVED

WDG base + 0xFE0

WDTPeriphID0

Peripheral identification register bits 7:0. See

Section 7.2.8: Watchdog peripheral identification

WDG base + 0xFE4

WDTPeriphID1

Peripheral identification register bits 15:8. See

Section 7.2.8: Watchdog peripheral identification

WDG base + 0xFE8

WDTPeriphID2

Peripheral identification register bits 23:16. See

Section 7.2.8: Watchdog peripheral identification

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