RM0352 datasheet(86/138 Pages) STMICROELECTRONICS

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I2C bus interface

RM0352

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DocID024647 Rev 1

10.2.10

I2C interrupt mask set/clear register (I2C_IMSCR)

Table 80. I2C interrupt mask set/clear register (I2C_IMSCR)

Address:

I2CBaseAddress + 0x2C

Type:

R/W

Reset:

0x00000000

I2C interrupt mask set/clear register (I2C_IMSCR)

15 14

13 12 11 10 9 8

RESERVED

Description:

C interrupt mask set/clear register

[30] TIMEOUTM: Timeout or Tlow error mask. TIMEOUTM enables the interrupt

bit.

TIMEOUT(SMBUS)

0: TIMEOUT interrupt is disabled, but checked internally.

1: TIMEOUT interrupt is enabled.

[29]

PECERRM: PEC error in reception mask. PECERRM enables the interrupt

bit.

PECERR(SMBUS)

0: PECERR interrupt is disabled.

1: PECERR interrupt is enabled.

[28]

MTDWSM: master transaction done without stop mask. MTDWSM enables

the interrupt bit.

MTDWS.

0: MTDWS interrupt is disabled.

1: MTDWS interrupt is enabled.

[25]

BERRM: bus error mask. BERRM enables the interrupt bit BERR.

0: BERR interrupt is disabled.

1: BERR interrupt is enabled.

[24]

MALM: master arbitration lost mask. MALM enables the interrupt bit MAL.

0: MAL interrupt is disabled.

1: MAL interrupt is enabled.

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