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RM0352 数据表(PDF) 44 Page - STMicroelectronics |
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RM0352 数据表(HTML) 44 Page - STMicroelectronics |
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44 / 138 page ![]() Watchdog timer (WDG) RM0352 44/138 DocID024647 Rev 1 7.2.7 Watchdog lock register WDT_LOCK Use of this register allows write access to all other registers to be disabled. This is to prevent rogue software from disabling the watchdog functionality. Writing a value of 0x1ACCE551 will enable write access to all other registers; writing any other value will disable write accesses. A read from this register will return only the least significant bit: • 0x0 indicates that write access is enabled (not locked) • 0x1 indicates that write access is disabled (locked). Table 40 shows the bit assignment of the WDT_LOCK register. Table 39. Watchdog lock register WDT_LOCK 7.2.8 Watchdog peripheral identification register WDTPeriphID0-3 The WDTPeriphID0-3 registers are four 8-bit registers, that span the address location 0xFE0 to 0xFEC. The registers are read-only. Table 41. Watchdog peripheral identification register WDTPeriphID0-3 - part 1 WDT_LOCK (WDT Base + 0xC00) Reset value: 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LOCKVAL R/W Table 40. WDT_LOCK register bit fields Bit field Function LOCKVAL Watchdog lock value When read, returns the lock status: 0x0: write access to all watchdog other registers is enabled (default). 0x1: write access to all watchdog other registers is disabled. When written, allows to enable or disable write access to all other watchdog registers: Writing 0x1ACCE551: Write access to all other registers is enabled. Writing any other value: Write access to all other registers is disabled. WDTPeriphID0 (WDT Base + 0xFE0) Reset value: 0x0000_0005 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED Part number 0 RR |
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