RM0352 datasheet(25/138 Pages) STMICROELECTRONICS

25 / 138 page

DocID024647 Rev 1

25/138

RM0352

Clock and reset management unit

137

Figure 3. Reset generation

5.3.2

Power-on reset

The power-on reset signal is the combination of the POR signal and the BOR signal

generated by the analog circuitry contained in the Brain device. The combination of these

signals is used to generate the PORESETn input to the Cortex-M0 which is used to reset

the debug access port (DAP) of the processor. It is also used to generate the DBGRESETn

signal which resets the debug logic of the Cortex-M0. The power-on reset signal also resets

the TAP controller of the Brain device.

5.3.3

ECC reset

The Brain device contains an error code correction circuitry associated with the program

memory. The ECC block takes the data read from the memories containing the ECC bits

and decodes the data to check the validity of the data being read. If a single bit error occurs

the ECC algorithm flags the error and automatically repairs the incorrect bit. If two data bits

are in error the ECC algorithm flags the double error and a reset is generated in the Brain

device. The reset will affect the Cortex-M0 and all its peripherals including the Flash

controller.

5.3.4

Watchdog reset

The Brain contains a watchdog circuit which may be used to recover from software crashes.

The watchdog contains a 32-bit down counter which generates an interrupt, if the interrupt is

not serviced the watchdog will generate a reset. The watchdog reset will reset the Flash

controller, the Cortex-M0 and all its peripherals but it will not reset the debug circuitry of the

Cortex-M0.

RM0352 数据表(PDF) 25 Page - STMicroelectronics