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RM0352 数据表(PDF) 101 Page - STMicroelectronics

部件名 RM0352
功能描述  Brain smart hub family
PDF  138 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

RM0352 数据表(HTML) 101 Page - STMicroelectronics

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RM0352
SPI (serial peripheral interface)
137
11.3
SPI registers
The SPI has following programmable parameters:
Master or slave mode
Enabling of operation
Frame format
Communication baud rate
Clock phase and polarity
Data widths from 4 to 16 bits wide
Interrupt masking.
The SPI base address block in the Brain memory map is 0xA300_0000.
Table 96 shows the PrimeCell SSP registers.
Table 96. PrimeCell SSP register summary
Offset
Name
Type
Reset
Width
Description
SSP Base + 0x00
SSPCR0
RW
0x0000
16
Control register 0, SSPCR0 - see
Section 11.4.1 on page 102
SSP Base + 0x04
SSPCR1
RW
0x0
4
Control register 1, SSPCR1 - see
Section 11.4.2 on page 104
SSP Base + 0x08
SSPDR
RW
0x----
16
Data register, SSPDR - see
Section 11.4.3
on page 104
SSP Base + 0x0C
SSPSR
RO
0x03
5
Status register, SSPSR - see
Section 11.4.4 on page 105
SSP Base + 0x10
SSPCPSR
RW
0x00
8
Clock prescale register, SSPCPSR - see
Section 11.4.5 on page 106
SSP Base + 0x14
SSPIMSC
RW
0x0
4
Interrupt mask set or clear register,
SSPIMSC - see
Section 11.4.6 on page
107
SSP Base + 0x18
SSPRIS
RO
0x8
4
Raw interrupt status register, SSPRIS -
see
Section 11.4.7 on page 108
SSP Base + 0x1C
SSPMIS
RO
0x0
4
Masked interrupt status register, SSPMIS -
see
Section 11.4.8 on page 108
SSP Base + 0x20
SSPICR
WO
0x0
4
Interrupt clear register, SSPICR - see
Section 11.4.9 on page 109
SSP Base + 0x24
-
-
-
-
RESERVED
SSP Base + 0x28 to 0x7C
-
-
-
-
RESERVED
SSP Base + 0x80 to 0x8C
-
-
-
-
RESERVED for test
SSP Base + 0x90 to 0xFCC
-
-
-
-
RESERVED
SSP Base + 0xFD0 to 0xFDC
-
-
-
-
RESERVED for future expansion
SSP base + 0xFEO
SSPPeriphID0
RO
0x22
8
Peripheral identification registers,
SSPPeriphID0-3 - see
Section 11.4.10 on
page 109
SSP base + 0xFE4
SSPPeriphID1
RO
0x10
8



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