RM0312 datasheet(53/275 Pages) STMICROELECTRONICS

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RM0312

Interrupt controller (ITC)

5.9.5

External interrupt control register 3 (EXTI_CR3)

Address offset: 0x02

Reset value: 0x00

5.9.6

External interrupt status register 1 (EXTI_SR1)

Address offset: 0x03

Reset value: 0x00

654

3210

Reserved

PDIS[1:0]

PBIS[1:0]

Bits 7:4 Reserved

Bits 3:2 PDIS[1:0]: Port D external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They

define the sensitivity of the Port D external interrupts, when EXTID for Port D[3:0] and/or Port D[7:4]

is enabled.

00: Falling edge and low level

01: Rising edge only

10: Falling edge only

11: Rising and falling edge

Bits 1:0 PBIS[1:0]: Port B external interrupt sensitivity bits

These bits can only be written when I1 and I0 in the CCR register are both set to 1 (level 3). They

define the sensitivity of the Port B external interrupts, when EXTIB for Port B[3:0] and/or PortB[7:4]

is enabled.

00: Falling edge and low level

01: Rising edge only

10: Falling edge only

11: Rising and falling edge

654

3210

P7F

P6F

P5F

P4F

P3F

P2F

P1F

P0F

rc_w1

Bits 7:0 PxF: Port A/B/C/D bit x external interrupt flag

These bits are set by hardware when an interrupt event occurs on the corresponding pin.They are

cleared by writing a ‘1’ by software.

0: No interrupt

1: External interrupt pending

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