RM0312 datasheet(45/275 Pages) STMICROELECTRONICS

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RM0312

Interrupt controller (ITC)

5.5.1

Concurrent interrupt management mode

In this mode, all interrupts are interrupt priority level 3 so that none of them can be

interrupted, except by a RESET, or TRAP.

The hardware priority is given in the following order from the lowest to the highest priority,

that is: MAIN, IT4, IT3, IT2, IT1, IT0, TRAP (same priority), and RESET.

Figure 8 shows an example of concurrent interrupt management mode.

Figure 8. Concurrent interrupt management

5.5.2

Nested interrupt management mode

In this mode, interrupts are allowed during interrupt routines. This mode is activated as soon

as an interrupt priority level lower than level 3 is set.

The hardware priority is given in the following order from the lowest to the highest priority,

that is: MAIN, IT4, IT3, IT2, IT1, IT0, and TRAP.

The software priority is configured for each interrupt vector by setting the corresponding

I1_x and I0_x bits of the ITC_SPRx register. I1_x and I0_x bits have the same meaning as

I1 and I0 bits of the CCR register (see Table 10).

Level 0 can not be programmed (I1_x=1, I0_x=0). In this case, the previously stored value is

kept. For example: if previous value is 0xCF, and programmed value equals 64h, the result

is 44h.

The RESET and TRAP vectors have no software priorities. When one is serviced, bits I1

and I0 of the CCR register are both set.

Caution:

If bits I1_x and I0_x are modified while the interrupt x is executed, the device operates as

follows: if the interrupt x is still pending (new interrupt or flag not cleared) and the new

software priority is higher than the previous one, then the interrupt x is re-entered.

Otherwise, the software priority remains unchanged till the next interrupt request (after the

IRET of the interrupt x).

During the execution of an interrupt routine, the HALT, POPCC, RIM, SIM and WFI

instructions change the current software priority till the next IRET instruction or one of the

previously mentioned instructions is issued. See Section 5.7 for the list of dedicated

interrupt instructions.

MAIN

IT4

IT2

IT1

TRAP

IT1

MAIN

IT0

SOFTWARE

3/0

11 / 10

RIM

IT3

PRIORITY

LEVEL

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