RM0312 datasheet(43/275 Pages) STMICROELECTRONICS

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RM0312

Interrupt controller (ITC)

Maskable interrupt sources

Maskable interrupt vector sources are serviced if the corresponding interrupt is enabled and

if its own interrupt software priority in ITC_SPRx registers is higher than the one currently

being serviced (I1 and I0 in CCR register). If one of these two conditions is not met, the

interrupt is latched and remains pending.

•

External interrupts

External interrupts can be used to wake up the MCU from Halt mode. The device

sensitivity to external interrupts can be selected by software through the External

Interrupt Control registers (EXTI_CRx).

When several input pins connected to the same interrupt line are selected

simultaneously, they are logically ORed.

When external level-triggered interrupts are latched, if the given level is still present at

the end of the interrupt routine, the interrupt remains activated except if it has been

inactivated in the routine.

•

Peripheral interrupts

peripheral interrupts cause the MCU to wake up from Halt mode. See the interrupt

vector table in the datasheet.

A peripheral interrupt occurs when a specific flag is set in the peripheral status register

and the corresponding enable bit is set in the peripheral control register.

The standard sequence for clearing a peripheral interrupt performs an access to the

status register followed by a read or write to an associated register. The clearing

sequence resets the internal latch. A pending interrupt (that is an interrupt waiting to be

serviced) is therefore lost when the clear sequence is executed.

5.3

Interrupts and low power modes

All interrupts allow the processor to exit from Wait mode.

Only a Reset or an event allows the processor to exit from Low power wait mode. This mode

is entered by executing a WFE instruction in Low power run mode. The wakeup by an event

makes the system go back to Low power run mode (refer to Section 9: Power management

for more details).

Only external and other specific interrupts allow the processor to exit from Halt and Active-

halt mode (see wakeup from halt and wakeup from Active-halt).

When several pending interrupts are present while waking up from Halt mode, the first

interrupt serviced can only be an interrupt with exit-from-Halt mode capability. It is selected

through the decision process shown in Figure 7. If the highest priority pending interrupt

cannot wake up the device from Halt mode, it will be serviced next.

If any internal or external interrupt (from a timer for example) occurs while the HALT

instruction is executing, the HALT instruction is completed but the interrupt invokes the

wakeup process immediately after the HALT instruction has finished executing. In this case

the MCU is actually waking up from Halt mode to Run mode, with the corresponding delay

of tWUH as specified in the datasheet.

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