RM0312 datasheet(76/275 Pages) STMICROELECTRONICS

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General purpose I/O ports (GPIO)

RM0312

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DocID022352 Rev 3

10.3

Port configuration and usage

An output data register (ODR), pin input register (IDR), data direction register (DDR) are

always associated with each port.

The control register 1 (CR1) and control register 2 (CR2) allow input/output options. An I/O

pin is programmed using the corresponding bits in the DDR, ODR, CR1 and CR2 registers.

Bit n in the registers corresponds to pin n of the Port.

The various configurations are summarized in Table 19.

Figure 13. GPIO block diagram

ODR REGISTER

DDR REGISTER

CR1 REGISTER

VDD

ALTERNATE

ENABLE

ALTERNATE

OUTPUT

PULL-UP

CONDITION

P-BUFFER

(see table below)

N-BUFFER

PULL-UP

(see table below)

ALTERNATE FUNCTION

INPUT TO ON-CHIP

VDD

DIODES

(see table below)

FROM

OTHER

BITS

EXTERNAL

TO INTERRUPT

INTERRUPT

CR2 REGISTER

PERIPHERAL

CONTROLLER

SLOPE

CONTROL

IDR REGISTER

(Read only)

OUTPUT

INPUT

PAD

PROTECTION

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