RM0312 datasheet(65/275 Pages) STMICROELECTRONICS

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RM0312

Clock control (CLK)

8.4.4

Configurable clock output register (CLK_CCOR)

Address offset: 0x05

Reset value: 0x10

654

3210

Reserved

CCOSLP[1:0]

CCOSEL[2:0]

CCOEN

Bits 7:6 Reserved

Bits 5:4 CCOSLP[1:0]: Configurable clock output buffer slope.

00: 400 kHz

01: 20 MHz

10: 10 MHz

11: 50 MHz

Bits 3:1 CCOSEL[2:0]: Configurable clock output selection.

These bits are written by software to select the source of the output clock available on the CLK_CCO

pin.

000: fMASTER

001: fMASTER/2

010: fMASTER/4

011: fMASTER/16

100: fPXS

101: fPXS/2

110: fPXS/4

111: fPXS/16

Note: To correctly output the ProxSense RC signal, the following sequence must be respected:

– Enable the PXS clock peripheral by setting bit PCKENR17 in the CLK_PCKENR1 register.

– Configure CCOSEL[2:0] and set bit CCO in the CLK_CCOR register.

– Enable the ProxSense peripheral by setting bit PXS_EN in the PXS_CR1 register.

Bit 0 CCOEN: Configurable clock output enable

This bit is set and cleared by software.

0: CCO clock output disabled

1: CCO clock output enabled

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