RM0312 datasheet(62/275 Pages) STMICROELECTRONICS

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Clock control (CLK)

RM0312

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DocID022352 Rev 3

8.1

Master clock (HSI clock)

The master clock of the system is a 16-MHz high-speed internal RC oscillator (HSI RC),

followed by a programmable prescaler.

The fHSI clock signal generated from the internal 16-MHz RC oscillator can then be divided

by a programmable divider (factor 1 to 8) to obtain fMASTER. This is programmed in the

Clock divider register (CLK_CKDIVR).

Note:

At startup the master clock source is automatically selected as HSI RC clock output divided

by 8 (HSI/8).

The HSI RC oscillator has the advantage of providing a 16-MHz master clock source with

50% duty cycle at low cost (no external components) and with a fast startup time.

The clock controller configures the master clock source as HSI RC clock output divided by 8

(fHSI/8), which helps ensure a safe startup in case of poor VDD conditions.

8.1.1

Peripheral clock gating (PCG)

Gating the clock to unused peripherals helps reduce power consumption. Peripheral clock

gating (PCG) mode selectively enables or disables the fMASTER clock connection to the

following peripherals at any time in run or slow mode:

•

TIM2

•

TIM3

•

TIM4

•

I2C

•

SPI

•

USART

•

AWU/BEEP (except LSI clock controlled by AWUEN bit in the Control/status register

(AWU_CSR) and by BEEPEN bit in the Beeper control/status register (BEEP_CSR)).

•

PXS (ProxSense)

•

WWDG

The Window Watchdog (WWDG) peripheral clock is the only one to be enabled by

default as it can be started by hardware if the corresponding option bit is set.

After a device reset, all peripheral clocks are disabled, except the WWDG clock. You can

enable the clock to any peripheral by setting the corresponding PCKEN bit in the Peripheral

clock gating register 1 (CLK_PCKENR1) or Peripheral clock gating register 2

(CLK_PCKENR2). To enable a peripheral, first enable the corresponding PCKEN bit in the

CLK_PCKENR registers and then set the peripheral enable bit in the peripheral control

registers.

To disable properly the peripheral, first disable the appropriate bit in the peripheral control

registers and then stop the corresponding clock.

The AWU counter is fed by the low speed internal specific clock (fLSI) different from fMASTER,

so that it continues to run even if the clock gating to this peripheral register is asserted. The

same is true for the beeper.

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