RM0312 datasheet(40/275 Pages) STMICROELECTRONICS

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Interrupt controller (ITC)

RM0312

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DocID022352 Rev 3

Interrupt controller (ITC)

5.1

ITC introduction

•

Management of hardware interrupts

–

Peripheral interrupt capability

•

Management of software interrupt (TRAP)

•

Nested or concurrent interrupt management with flexible interrupt priority and level

management:

–

Up to 4 software programmable nesting levels

–

22 interrupt vectors fixed by hardware

–

2 non maskable events: RESET, TRAP

This interrupt management is based on:

•

Bit I1 and I0 of the CPU Condition Code register (CCR)

•

Software priority registers (ITC_SPRx)

•

Reset vector located at 0x00 8000 at the beginning of program memory. The Reset

initialization routine is programmed in ROM by STMicroelectronics.

•

Fixed interrupt vector addresses located at the high addresses of the memory map

(0x00 8004 to 0x00 807C) sorted by hardware priority order.

5.2

Interrupt masking and processing flow

The interrupt masking is managed by bits I1 and I0 of the CCR register and by the

ITC_SPRx registers which set the software priority level of each interrupt vector (see

Table 8). The processing flow is shown in Figure 6.

When an interrupt request has to be serviced:

Normal processing is suspended at the end of the current instruction execution.

The PC, X,Y, A and CCR registers are saved onto the stack.

Bits I1 and I0 of CCR register are set according to the values in the ITC_SPRx registers

corresponding to the serviced interrupt vector.

The PC is then loaded with the interrupt vector of the interrupt to service and the first

instruction of the interrupt service routine is fetched (refer to the datasheet interrupt

mapping table for details on vector addresses).

The interrupt service routine should end with the IRET instruction which causes the content

of the saved registers to be recovered from the stack. As a consequence of the IRET

instruction, bits I1 and I0 are restored from the stack and the program execution resumes.

Table 8. Software priority levels

Software priority

Level

Level 0 (main)

Low

High

Level 1

Level 2

Level 3 (= software priority disabled)

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