RM0312 datasheet(57/275 Pages) STMICROELECTRONICS

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RM0312

Reset (RST) and voltage detection

There are six reset sources:

•

External reset through the NRST pin (this pin can also be configured as general

purpose output)

•

Power-on reset (POR)

•

Independent watchdog reset (IWDG)

•

Window watchdog (WWDG)

•

SWIM reset

•

Illegal opcode reset

These sources act on the RESET pin. The RESET service routine vector is fixed at address

0x8000 in the memory map.

Figure 11. Reset circuit

7.1

“Reset state” and “under reset” definitions

When a reset occurs, there is a reset phase from the external pin pull-down to the internal

reset signal release. During this phase, the microcontroller sets some hardware

configurations before going to the reset vector.

At the end of this phase, most of the registers are configured with their “reset state” values.

During the reset phase, i.e. “under reset”, some pin configurations may be different from

their “reset state” configuration.

7.2

External reset (NRST pin)

7.2.1

Asynchronous external reset description

The NRST pin is both an input and an open-drain output with integrated RPU weak pull-up

resistor.

A minimum of 300 ns low pulse on the NRST pin is needed to generate an external reset.

The reset detection is asynchronous and therefore the MCU can enter reset even in Halt

mode.

The NRST pin also acts as an open-drain output for resetting external devices.

NRST

RPU

VDD

Pulse

Generator

SWIM RESET

EXTERNAL

RESET

(min 20 µs)

SYSTEM NRESET

ILLEGAL OPCODE RESET

IWDG RESET

Filter

(typ 40 k

Ω)

POR RESET

WWDG RESET

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