RM0312 datasheet(96/275 Pages) STMICROELECTRONICS

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Window watchdog (WWDG)

RM0312

96/275

DocID022352 Rev 3

14.6

Hardware watchdog option

If hardware watchdog is selected by option byte, the watchdog is always active and the

WDGA bit in the WWDG_CR register is not used. Refer to the option byte description in the

datasheet.

14.7

WWDG interrupts

None.

14.8

WWDG registers

14.8.1

Control register (WWDG_CR)

Address offset: 0x00

Reset value: 0x7F

14.8.2

Window register (WWDG_WR)

Address offset: 0x01

Reset value: 0x7F

654

3210

WDGA

Bit 7 WDGA: Activation bit(1)

This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog

can generate a reset.

0: Watchdog disabled

1: Watchdog enabled

Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB)

These bits contain the value of the watchdog counter. It is decremented every 12288 fMASTER cycles

(approximately). A reset is produced when it rolls over from 0x40 to 0x3F (T6 becomes cleared).

1. This bit is not used if the hardware watchdog option is enabled by option byte.

654

3210

Reserved

Bit 7 Reserved

Bits 6:0 W[6:0]: 7-bit window value

These bits contain the window value to be compared to the downcounter.

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