RM0312 datasheet(94/275 Pages) STMICROELECTRONICS

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Window watchdog (WWDG)

RM0312

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DocID022352 Rev 3

The application program must write in the WWDG_CR register at regular intervals during

normal operation to prevent an MCU reset. This operation must occur only when the counter

value is lower than the window register value. The value to be stored in the WWDG_CR

•

Enabling the watchdog:

When software watchdog is selected (by option byte), the watchdog is disabled after a

reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot

be disabled again except by a reset.

When hardware watchdog is selected (by option byte), the watchdog is always active

and the WDGA bit is not used.

•

Controlling the downcounter:

This downcounter is free-running: It counts down even if the watchdog is disabled.

When the watchdog is enabled, the T6 bit must be set to prevent generating an

immediate reset.

The T[5:0] bits contain the number of increments which represents the time delay

before the watchdog produces a reset. The timing varies between a minimum and a

maximum value due to the unknown status of the prescaler when writing to the

WWDG_CR register (see Figure 17).

The window register (WWDG_WR) contains the high limit of the window: To prevent a

reset, the downcounter must be reloaded when its value is lower than the window

process.

Note:

The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is

cleared).

•

Watchdog reset on halt option

If the watchdog is activated and the watchdog reset on halt option is selected, then the

HALT instruction will generate a reset.

14.4

How to program the watchdog timeout

The formula below can be used to calculate the WWDG timeout, tWWDG, expressed in ms:

where TfMASTER is the peripheral clock period expressed in ms

Warning:

When writing to the WWDG_CR register, always write 1 in the

T6 bit to avoid generating an immediate reset.

tWWDG

MASTER

12288

T5:0

[] 1

()

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