RM0312 datasheet(80/275 Pages) STMICROELECTRONICS

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General purpose I/O ports (GPIO)

RM0312

80/275

DocID022352 Rev 3

10.9

GPIO registers

The bit of each port register drives the corresponding pin of the port.

10.9.1

Port x output data register (Px_ODR)

Address offset: 0x00

Reset value: 0x00

10.9.2

Port x pin input register (Px_IDR)

Address offset: 0x01

Reset value: 0xXX

Note:

Px_IDR reset value depends on the external circuitry.

654

3210

ODR7

ODR6

ODR5

ODR4

ODR3

ODR2

ODR1

ODR0

Bits 7:0 ODR[7:0]: Output data register bits

Writing to the ODR register when in output mode applies a digital value to the I/O through the latch.

Reading the ODR returns the previously latched value in the register.

In Input mode, writing in the ODR register, latches the value in the register but does not change the

pin state. The ODR register is always cleared after reset. Bit read-modify-write instructions (BSET,

BRST) can be used on the DR register to drive an individual pin without affecting the others.

654

3210

IDR7

IDR6

IDR5

IDR4

IDR3

IDR2

IDR1

IDR0

rrr

rrrr

Bits 7:0 IDR[7:0]: Pin input values

The pin register can be used to read the pin value irrespective of whether port is in input or output

mode. This register is read-only.

0: Low logic level

1: High logic level

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