RM0312 datasheet(99/275 Pages) STMICROELECTRONICS

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RM0312

Independent watchdog (IWDG)

101

Timeout period

The maximum timeout period can be configured through the IWDG_PR and IWDG_RLR

registers. It is determined by the following equation:

where:

T = Maximum timeout period

TLSI = 1/fLSI

P = 2 (PR[2:0] + 2)

R = RLR[7:0]+1

The IWDG counter must be refreshed by software before this timeout period expires.

Otherwise, an IWDG reset will be generated after the following delay has elapsed since the

last refresh operation:

D = T + 3 x TLSI

where D= delay between the last refresh operation and the IWDG reset.

Using the IWDG in Halt/Active-halt mode

The IWDG can continue to work in Halt or Active-halt mode, depending on the configuration

of the IWDG_HALT option byte. In this case, it can wake up the device from one of these

modes. For more details, please refer to the Option Byte description in the datasheet.

Note:

The application must configure correctly the IWDG timeout and refresh the IWDG counter

before executing the HALT instruction, to avoid unexpected IWDG reset.

Table 29. Min/Max IWDG timeout (LSI clock frequency = 38 kHz)

Prescaler divider

PR[2:0] bits

Timeout (ms)

RL[7:0]= 0x00

RL[7:0]= 0xFF

0.11

26.95

0.21

53.89

/16

0.42

107.79

/32

0.84

215.58

/64

1.68

431.16

/128

3.37

862.32

/256

6.74

1724.63

TTLSI P

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