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RM0312 数据表(PDF) 103 Page - STMicroelectronics |
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RM0312 数据表(HTML) 103 Page - STMicroelectronics |
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103 / 275 page  DocID022352 Rev 3 103/275 RM0312 Timer overview 170 16.2 Glossary of timer signal names Table 33. Glossary of internal timer signals Internal signal name Description Related figures BI Break interrupt Figure 19: TIMx general block diagram on page 106 CCiI, CC1I, CC2I, CC3I, CC4I Capture/compare interrupt CK_CNT Counter clock Figure 23: Counter update when ARPE=0 (ARR not preloaded) with prescaler = 2 on page 110 CK_PSC Prescaler clock CNT_EN Counter enable CNT_INIT Counter initialize Figure 32: TI2 external clock connection example on page 116 ETR External trigger from TIMx_ETR pin Figure 34: External trigger input block on page 117 ETRF External trigger filtered ETRP External trigger prescaled fMASTER Timer peripheral clock from clock controller (CLK) Figure 12: Clock structure on page 61 ICi, IC1, IC2 Input capture Figure 51: Input stage of TIM 1 channel 1 on page 130 ICiPS, IC1PS, IC2PS Input capture prescaled ITRx, ITR1, ITR2, ITR3 Internal trigger input tied to TRGO of other TIM timers Figure 19: TIMx general block diagram on page 106 MATCH1 Compare match Figure 41: Trigger/master mode selection blocks on page 122 and Section 17.7.2: Control register 2 (TIMx_CR2) on page 145 OCi, OC1, OC2 Timer output channel Figure 17.5.5: Forced output mode on page 133 OCiREF, OC1REF, OC2REF Output compare reference signal TGI Trigger interrupt Figure 30: Clock/trigger controller block diagram on page 115 TIi, TI1, TI2 Timer input Figure 51: Input stage of TIM 1 channel 1 on page 130 TIiF, TI1F, TI2F Timer input filtered TI1F_ED Timer input filtered edge detector TIiFPx, TI1FP1, TI1FP2, TI2FP1, TI2FP2 Timer input filtered prescaled TRC Trigger capture TRGI Trigger input to clock/trigger/slave mode controller Figure 31: Control circuit in normal mode, fMASTER divided by 1 on page 116 TRGO Trigger output tied to trigger input ITRx of other timers Figure 19: TIMx general block diagram on page 106 |
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