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RM0312 数据表(PDF) 101 Page - STMicroelectronics |
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RM0312 数据表(HTML) 101 Page - STMicroelectronics |
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101 / 275 page  DocID022352 Rev 3 101/275 RM0312 Independent watchdog (IWDG) 101 15.3.3 Reload register (IWDG_RLR) Address offset: 0x02 Reset value: 0xFF 15.3.4 IWDG register map and reset values 7 654 3210 RL[7:0] rw Bits 7:0 RL[7:0]: Watchdog counter reload value These bits are write access protected (see Section 15.2). They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to Table 29. Table 30. IWDG register map Address offset Register name 765 432 10 0x00 IWDG_KR Reset value KEY[7:0] xxxxxxxx 0x01 IWDG_PR Reset value - 0 - 0 - 0 - 0 - 0 PR2[2:0] 000 0x02 IWDG_RLR Reset value RL7[7:0] 11111111 |
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