RM0312 datasheet(41/275 Pages) STMICROELECTRONICS

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RM0312

Interrupt controller (ITC)

Figure 6. Interrupt processing flowchart

Caution:

If the interrupt mask bits I0 and I1 are set within an interrupt service routine (ISR) with the

instruction SIM, removal of the interrupt mask with RIM causes the software priority to be

set to level 0.

To restore the correct priority when disabling and enabling interrupts inside an ISR, follow

the procedures presented in Table 8 for disabling and enabling the interrupts.

5.2.1

Servicing pending interrupts

Several interrupts can be pending at the same time. The interrupt to be taken into account is

determined by the following two-step process:

The highest software priority interrupt is serviced.

If several interrupts have the same software priority then the interrupt with the highest

hardware priority is serviced first.

When an interrupt request is not serviced immediately, it is latched and then processed

when its software priority combined with the hardware priority becomes the highest one.

Note:

The hardware priority is exclusive while the software one is not. This allows the previous

process to succeed with only one interrupt.

RESET and TRAP are considered as having the highest software priority in the decision

process.

“IRET”

RESTORE PC, X, Y, A, CCR

STACK PC, X, Y, A, CCR

LOAD I1:0 FROM INTERRUPT SW REG.

FETCH NEXT

RESET

TRAP

PENDING

INSTRUCTION

I1:0

FROM STACK

LOAD PC FROM INTERRUPT VECTOR

Interrupt has the same or a

lower software priority

THE INTERRUPT

STAYS PENDING

than current one

EXECUTE

INSTRUCTION

INTERRUPT

Table 9. Interrupt enabling/disabling inside an ISR

Disabling the interrupts

Enabling the interrupts

#asm

PUSH CC

POP ISR_CC(1)

SIM

#endasm

1. IRS_CC is a variable which stores the current value of the CC register.

#asm

PUSH ISR_CC(1)

POP CC

#endasm

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