RM0312 datasheet(193/275 Pages) STMICROELECTRONICS

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RM0312

Inter-integrated circuit (I2C) interface

200

19.7.9

Status register 2 (I2C_SR2)

Address offset: 0x08

Reset value: 0x00

654

3210

Reserved

WUFH

Reserved

OVR

ARLO

BERR

rc_w0

Bits 7:6 Reserved

Bit 5 WUFH: Wakeup from Halt

0: no wakeup from Halt mode

1: 7-bit address or header match in Halt mode (slave mode) or Halt entered when in master mode.

Note: This bit is set asynchronously in slave mode (during HALT mode). It is set only if ITEVTEN = 1.

–

cleared by software writing 0, or by hardware when PE=0.

Bit 4 Reserved

Bit 3 OVR: Overrun/underrun

0: No overrun/underrun

1: Overrun or underrun

–

Set by hardware in slave mode when NOSTRETCH=1 and:

–

In reception when a new byte is received (including ACK pulse) and the DR register has not

been read yet. New received byte is lost.

–

In transmission when a new byte should be sent and the DR register has not been written

yet. The same byte is sent twice.

Cleared by software writing 0, or by hardware when PE=0.

Note: if the DR write occurs very close to the SCL rising edge, the sent data is unspecified and a hold

timing error occurs.

Bit 2 AF: Acknowledge failure.

0: No acknowledge failure

1: Acknowledge failure

–

Set by hardware when no acknowledge is returned.

–

Cleared by software writing 0, or by hardware when PE=0.

Bit 1 ARLO: Arbitration lost (master mode)

0: No Arbitration lost detected

1: Arbitration lost detected

Set by hardware when the interface loses the arbitration of the bus to another master.

–

Cleared by software writing 0, or by hardware when PE=0.

After an ARLO event the interface switches back automatically to Slave mode (MSL=0).

Bit 0 BERR: Bus error

0: No misplaced Start or Stop condition

1: Misplaced Start or Stop condition

–

Set by hardware when the interface detects a SDA rising or falling edge while SCL is high,

occurring in a non-valid position during a byte transfer.

–

Cleared by software writing 0, or by hardware when PE=0.

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