RM0319 datasheet(289/368 Pages) STMICROELECTRONICS

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RM0319

JPEG codec accelerator (JPGC)

Doc ID 022640 Rev 3

289/368

The main building blocks of the JPGC are five:

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The Codec Core

●

The Codec Controller

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The DMA controller (DMAC)

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The FIFO buffers (FIFO in and FIFO out)

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The internal memories

26.4.1

Codec core

The Codec core implements all the steps necessary to encode and decode image data

according to the JPEG baseline algorithm as specified in ISO/IEC 10918-1. It is specifically

designed to accelerate entropy-coded segment (ECS) encoding and decoding, because this

forms the most computing-intensive part of the baseline JPEG algorithm.

The Codec Core can enable/disable header processing. If disabled, only the ECS data is

generated/decoded. Support for restart markers is also provided: the Codec core

recognizes them in the encoded stream when decoding, and can optionally insert them

when encoding.

JPEG encoded data streams decoded by the Codec core must be compliant with the

interchange format syntax specified in the ISO/IEC 10918-1. Also JFIF images, the de facto

standard used to encoded JPEG images, is supported.

Before any coding process can start, the Codec core, together with the dmac and the

internal memories, must be programmed by writing to the corresponding registers.

The Codec Core receives from the FIFO in buffer its input data, which can be either a

sequence of Minimum Coded Units (MCU) (if the JPGC is used as an encoder from YUV

MCUs to JPEG) or a stream of Entropy Coded Segments (ECS) (if the JPGC is used as a

decoder from JPEG to YUV MCUs). Conversely, output data from the codec core are sent to

the FIFO Out buffer as an ECS stream (resp. MCU sequence), whenever the JPGC is

working as an encoder (resp. decoder).

26.4.2

Codec controller

The codec controller manages the data flow between the codec core and the FIFO buffers

between the FIFO buffers and the external RAM. In order to accomplish the latter task, it

uses the DMAC to perform fast data transfers.

Due to area optimization of the JPGC block, encoding and decoding operations performed

by the Codec Core cannot be simultaneous. Thus the Codec Controller is in charge to

assure that only a given data path (JPEG data from RAM -> JPGC -> YUV MCU data to

RAM, or the opposite) is active at a certain time.

26.4.3

DMAC

The DMA controller is used by the codec controller to perform fast data transfers from/to

external RAM to/from the internal FIFO buffers. The DMAC has to be programmed with the

correct transfer parameters, before any coding process can start. See also Chapter 36:

DMA controller (DMAC), for an in-depth description of the direct memory access block.

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