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数据搜索系统，热门电子元器件搜索 |
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RM0319 数据表(PDF) 292 Page - STMicroelectronics |
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RM0319 数据表(HTML) 292 Page - STMicroelectronics |
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292 / 368 page  Digital audio port (I2S) RM0319 292/368 Doc ID 022640 Rev 3 27.4 Functional description Figure 103. I2S block diagram 27.4.1 Transmit channels I2S has one stereo I2S transmit (TX) channel. This channel operates in master mode. Stereo data pairs (such as, left and right audio data) written to a TX channel register are shifted out serially on the serial data out line I2S_TX. The shifting is timed with respect to the serial clock I2S_CLK and the word select line I2S_LR. Note: The clock generation block must be disabled prior to any changes to I2S_CLK gating value. (refer to RM0321: SPEAr320S address map and registers) 27.4.2 Receive channels I2S has one stereo I2S receive (RX) channel. This channel operates in master mode. Stereo data pairs (such as, left and right audio data) are received serially from a data input line I2S_RX. These data words are stored in RX FIFOs until they are read by software. The receiving is timed with respect to the serial clock (I2S_CLK) and the word select line (I2S_LR). See also: Section 27.7.2: Using the I2S receiver (Rx mode) APB interface DMAC REQ/CLR Interrupts I2S Master audio_over_samp_clk I2S_CLK I2S_TX I2S_LR I2S_RX Transmit channel 0 Receive channel 0 Left FIFO Left FIFO Right FIFO Right FIFO |
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