RM0319 datasheet(318/368 Pages) STMICROELECTRONICS

318 / 368 page

System controller (SYSCTR)

RM0319

318/368

Doc ID 022640 Rev 3

If the NORMAL mode control bit is not set, then the system moves into the “Switch from

PLL” transition state.

XTAL control transition state, XTAL CTL

XTAL control transition state is used to initialize the crystal oscillator. While in this state, both

the system clocks and the system controller clock are driven from a low-frequency oscillator.

The system moves into the Switch to XTAL transition state when the crystal oscillator output

is stable. This is indicated when either the XTAL timeout defined in the XTAL control register

expires (when the XTALTIMEEN input is valid) or by the XTALON input being set to logic ‘1’.

Switch to XTAL transition state, SW TO XTAL

Switch to XTAL transition state is used to initiate the switching of the system clock source

from the slow speed oscillator to the crystal oscillator. The system moves into the SLOW

mode when the XTALSW input is set to logic ‘1’, to indicate that the clock switching is

complete.

Switch from XTAL transition state (SW from XTAL)

The “Switch from XTAL” transition state is entered when moving from SLOW to DOZE mode.

It is used to initiate the switching of the system clock source from the crystal oscillator to the

low speed oscillator. The system moves into the DOZE mode when the XTALSW input is set

to PLL control transition state (PLL CTL)

PLL control transition state, PLL CTL

The “PLL control” transition state is used to initialize the PLL. While in this state, both the

system clocks and the system controller clock are driven by the output of the crystal

oscillator.

The system moves then into the “Switch to PLL” transition state when the PLL timeout

defined in the PLL control register (SCPLLCTRL register) expires (when the PLLTIMEEN

input is invalid) and if the PLLON input is set to logic1.

Switch to PLL transition state (SW to PLL)

The “Switch to PLL” transition state is used to initiate the switching of the system clock

source from the crystal oscillator to the PLL output.

The system moves then into the NORMAL mode when the PLLSW input is set to logic ‘1’ to

indicate that the clock switching is complete.

Switch from PLL transition state (SW from PLL)

The “Switch from PLL” transition state is entered when moving from NORMAL to SLOW

mode. It is used to initiate the switching of the clock sources from the PLL to the crystal

oscillator output.

The system moves then into the SLOW mode when the PLLSW input is set to logic ‘0’ to

indicate that the clock switching is complete.

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