RM0319 datasheet(320/368 Pages) STMICROELECTRONICS

320 / 368 page

System controller (SYSCTR)

RM0319

320/368

Doc ID 022640 Rev 3

29.3.3

Interrupt response mode

To enable the best possible response to interrupts, the current mode bits can be modified by

hardware in the system control register after an interrupt has been generated. This enables,

for example, the state machine to move from DOZE mode to NORMAL mode after an

interrupt.

The interrupt response functionality is controlled by the interrupt mode control register

(SCIMCTRL), which defines if the functionality has been enabled, the mode of operation

that is required following an interrupt, what type of interrupt is permitted to enable the

interrupt response mode, an interrupt mode status bit and clear mechanism.

Note:

It is not possible for the interrupt response mode to slow the system operating speed, for

example, changing mode from NORMAL to SLOW.

The interrupt response mode is cleared by writing a 1‘b0 to the interrupt mode control

29.3.4

Reset control

The reset control is used to request a soft reset to be generated by asserting the

SOFTRESREQ output for a single SCLK cycle when any value is written to the reset status

29.3.5

Core clock control

To enable the software to control the relative frequency of the core clock (CLK) and the bus

clock (HCLK), the system controller provides access to the HCLKDIVSEL[2:0] output

through the system control register (namely the 3 bit field HCLKDivSel of the SCCTRL

These output signals are intended for use by the clock generation logic to control the

generation of the CLK/HCLK clock source and the HCLKEN input. To prevent spurious

change of the CLK/HCLK clock ratio, the HCLKDIVSEL output is only allowed to change

when the system mode control state machine is in a stable state, that is, the actual system

mode matches the required system mode.

29.3.6

Watchdog module clock enable generation

Enable signals are generated by the system controller to allow the watchdog module to be

clocked at a rate that is independent of the system clock PCLK. In particular, the enable

signals are generated by sampling a free-running, constant frequency input clock (REFCLK)

and generating an active high pulse for a single PCLK clock cycle on each rising edge of the

input clock (REFCLK). Since PCLK is used to sample REFCLK the frequency of PCLK must

be at least double.

The supported module enable signals are:

●

WDCLKEN for the watchdog module clock enable.

The enable signal for the watchdog module is generated from the REFCLK input (24 MHz

crystal clock), as defined in the system control register (SCCTRL).

Additionally, to enable the watchdog module to be clocked directly at the system clock rate, it

is also possible to selectively force the enable outputs high setting to 1 SSCTRL[23]

(WDogEnOv). The watchdog clock enable output can be forced inactive by de-asserting the

WDEN input. The WDEN input is driven low when the processor is in debug state.

RM0319 数据表(PDF) 320 Page - STMicroelectronics

RM0319 数据表(HTML) 320 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载