RM0319 datasheet(324/368 Pages) STMICROELECTRONICS

324 / 368 page

Power, reset and clock control

RM0319

324/368

Doc ID 022640 Rev 3

In this state, the CPU is running with the RTC or the main oscillator, according to the bit set

in PRPH_CLK_CFG.rtc_disable. After reset, the main oscillator is selected (which allows to

have systems without RTC oscillator).

You can select a division of main oscillator frequency through

CORE_CLK_CFG.osci24_div_en to enable and CORE_CLK_CFG.osci24_div_ratio bits to

select ratio.

Using the RTC oscillator, you can achieve better results in terms of power consumption.

Code execution

In DOZE state, the code has to run from internal memory (Boot ROM, internal RAM, Cache

and TCM if present) or from external memory Serial Flash or DRAM. To run from DRAM,

you must use PLL2 for the SDRAM controller (asynchronous DRAM mode) with a frequency

higher than the minimum supported by used DRAM.

It is also recommended, if wake-up response allows it, to put DDR in self refresh mode.

The transition to another state is software-controlled through SCCTRL ModeCtrl bits. It

allows to program directly in NORMAL state, in this case the hardware will execute

transitioning as several steps. Less than five clock cycles are required to change from one

state to another.

30.1.3

SLOW

In SLOW mode, both the system clocks and the system controller clock are driven from the

output of the crystal oscillator.

If NORMAL mode is required, the system moves into the “PLL control” transition state. If

neither the SLOW nor the NORMAL mode control bits are set, the system moves into the

“Switch from XTAL” transition state.

You

can

select

division

the

main

oscillator

frequency

through

CORE_CLK_CFG.osci24_div_en to enable and CORE_CLK_CFG.osci24_div_ratio bits to

select ratio.

In SLOW state, there are the same constrains of DOZE state for code execution.

The transition to another state is software-controlled through SCCTRL Mode Ctrl bits.

It is allowed to program DOZE state and nothing else is required.

To go in NORMAL state, you must program PLL1 at the desired frequency. PLL has to be

stable before switching to NORMAL. To achieve this, two ways are possible:

●

By software, verifying PLL1_CTR.pll_lock bit, applicable if Dither is disabled

(PLL1_CTR.pll_control1.DitherMode).

●

By hardware. An intermediate hardware state waits for PLL stabilization using a pre-

programmed delay, use SCPLLCTRL.PllTime for time delay with SCPLLCTRL PllOver

disabled. See formula in Section 30.4: Reset to calculate the proper delay.

30.1.4

NORMAL

In NORMAL mode, both the system clocks and the system controller clock are driven from

the output of PLL.

If the NORMAL mode control bit is not set, then the system moves into the “Switch from

PLL” transition state.

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