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RM0319 数据表(PDF) 322 Page - STMicroelectronics |
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RM0319 数据表(HTML) 322 Page - STMicroelectronics |
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322 / 368 page  Power, reset and clock control RM0319 322/368 Doc ID 022640 Rev 3 Figure 108. System operation states Table 115. Power state for synchronous DRAM system (DRAM clocked by PLL1) State ARM ARM clock DRAM Possible code execution memory SLEEP Hibernate Off Self refresh None DOZE Running Running RTC Osc MAIN Osc(PLL off) Self refresh Self refresh Internal memory Internal memory SLOW Running MAIN Osc.(PLLoff) Self refresh Internal memory NORMAL Running PLL1 (Up to 333 MHz) Active Internal memory and external DRAM Table 116. Power state for asynchronous DRAM system (DRAM clocked by PLL2) State ARM ARM clock DRAM Possible code execution memory SLEEP Hibernate Hibernate off off Self refresh Active None None DOZE Running RTC Osc. Self refresh Internal memory Running RTC Osc Active Internal memory and external DRAM Running MAIN Osc. (PLL off) Self refresh Internal memory Running MAIN Osc.(PLL off) Active Internal memory and external DRAM DOZE SLOW SLEEP NORMAL Performance Consumption IRQ, FIQ and RESET Dynamic Frequency Scaling |
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