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RM0319 数据表(PDF) 329 Page - STMicroelectronics |
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RM0319 数据表(HTML) 329 Page - STMicroelectronics |
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329 / 368 page ![]() RM0319 Power, reset and clock control Doc ID 022640 Rev 3 329/368 30.3.3 Combining frequency scalling and clock techniques In NORMAL state, the best active power saving is obtained by combining the power management techniques previously described. These techniques reduce the power consumption of a device allowing a fast response to a critical task (that can be performed always at maximum frequency, if needed). 30.3.4 Statically frequency selection and clock switching OFF With this technique, you can define statically, based on performance defined in the manufacturing process, the frequency and activate only the modules requested by the application. This technique is easier from the designer’s point of view for software development and offers a well known consumption. It is recommended that when the performance required is without critical task, it is sufficient to guarantee an average power computation. This technique should be applied when a constant consumption is requested by the system. It is useful when USB ports are not requested switch of USB PLL (PLL3) and peripheral clock could be attached to PLL1, with the right prescaler. Also PLL2 should be OFF in synchronous mode. Flash serial (SMI) IrDA PLL1 Internal ROM JPEG codec PLL2 DMA I2C PLL3 Table 118. Modules supporting DCS technique Module Module Module |
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