RM0319 datasheet(330/368 Pages) STMICROELECTRONICS

330 / 368 page

Power, reset and clock control

RM0319

330/368

Doc ID 022640 Rev 3

30.4

Reset

30.4.1

Main reset (MRESET)

To ensure the system starts correctly after power on, the external reset pin MRESET must

be held low by hardware until the power supply is stable.

30.4.2

Software reset control

A system reset can be generated by writing any value to the system status register

(SCSYSSTAT).

The on-chip peripherals can be reset individually by writing to the corresponding control bits

in the MISC PERIP1_SOF_RST and MISC RAS_SOF_RST registers.

30.4.3

Watchdog reset

Refer to Section 34: Watchdog timer (WDT).

30.5

Clock control

The clock control system block generates all the internal clock signals and controls the

system reset. Several synthesizers provide different frequencies for the various IPs. It

provides fully programmable control of clock and reset signals for all the slave blocks

allowing sophisticated power management

30.5.1

Main clocks

The main clocks, at default operating frequency, are:

●

SYS_CLK and CPU_CLK @ up to 333 MHz for the system and CPU

●

HCLK @ 166 MHz for the AHB Bus and AHB peripherals

●

PCLK @ 83 MHz for the APB Bus and APB peripherals

●

DDR_CLK @ 100-333 MHz for DDR memory interface

●

CLK12MHz, CLK30MHz and CLK48MHz for the USB controllers

The above frequencies are the maximum allowed values. All these clocks are generated by

three PLLs as shown in Figure 110 and Figure 111.

See also Section 30.5.2: PLL programming.

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