RM0319 datasheet(331/368 Pages) STMICROELECTRONICS

331 / 368 page

RM0319

Power, reset and clock control

Doc ID 022640 Rev 3

331/368

Figure 110. Main clock sources

The following registers in the MISC register block are used to configure and control the

clocks:

●

PLL1_CTR, PLL1_FRQ, PLL1_MOD,

●

PLL2_CTR, PLL2_FRQ, PLL2_MOD,

●

PLL_CLK_CFG, CORE_CLK_CFG,

●

PRPH_CLK_CFG, PERIP1_CLK_ENB, RAS_CLK_ENB,

●

PRSC1_CLK_CFG, PRSC2_CLK_CFG, PRSC3_CLK_CFG, AMEM_CFG_CTRL,

●

IRDA_CLK_SYNT_CFG, UART0_CLK_CFG, MAC_CLK_SYNT_CFG,

RAS_CLK_SYNT1_CFG, RAS_CLK_SYNT2_CFG, RAS_CLK_SYNT3_CFG,

RAS_CLK_SYNT4_CFG

The following registers in the system controller register block are also used to configure and

control the clocks (see also Chapter 29: System controller (SYSCTR)):

●

SCCTRL SCXTALCTRL, SCPLLCTRL

24 MHz

OSC

PLL2

MISC PLL_CLK _CFG

PL_CLK3

MCLK_XI

MCLK_XO

PLL1

MISC PLL1_FREQ register(0x0C)

MISC PLL1_MOD register (0x10)

MISC PLL1_CTR register (0x08)

MISC PLL_CLK _CFG

PL_CLK4

PLL3

CLK12 MHz

PLL2_CLKOUT

100- 333 MHz

32 KHz

OSC

RTC_XI

RTC_XO

up to 333 MHz

up to 32.768 kHz

up to 24 MHz

CPU_CLK

CLK30 MHz

CLK48 MHz

SYS_CLK

/2, /4, /16, /32

system state control

logic

System controller

MISC CORE_CLK_CFG register (0x24)

MISC PLL2_FREQ register(0x18)

MISC PLL2_MOD register (0x1C)

MISC PLL2_CTR register (0x14)

(input to multiplexer

for DDR_CLK)

(input to prescalers

for HCLK and PCLK)

Divider

RM0319 数据表(PDF) 331 Page - STMicroelectronics

RM0319 数据表(HTML) 331 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载