RM0319 datasheet(334/368 Pages) STMICROELECTRONICS

334 / 368 page

Power, reset and clock control

RM0319

334/368

Doc ID 022640 Rev 3

●

SYS_CLK and CLK_CPU clock sources

When the system switches from NORMAL, SLOW, DOZE or SLEEP mode, the system clock

source is selected automatically (multiplexer M2 in Figure 110 on page 331.).

Depending on the state machine (see Chapter 29: System controller (SYSCTR) for full

details) the system clock (SYS_CLK) and the CPU clock (CPU_CLK) can be derived from

the following sources:

●

External oscillator (24 MHz) (divided by 2, 4, 16 or 32)

●

PLL1 (up to 333 MHz)

●

RTC crystal (32.768 kHz)

The selection depends also on the value programmed in the rtc_disable bit in the MISC

PRPH_CLK_CFG register.

By programming the miscellaneous registers, you can define:

●

the output frequency of PLL1 (used in NORMAL mode)

●

the divider for 24 MHz oscillator (used in SLOW and DOZE mode).

30.5.4

DDR memory controller clock

The multiport memory controller (MPMC) uses the HCLK to synchronize the internal bus

access and uses another clock source, which can be chosen between PLL1 or PLL2

(setting the MISC registers), for the external DDR memory interface.

The two clock domains can be synchronous or asynchronous. Having the two clock domains

asynchronous offers more flexibility in the system definition, but also adds more latency due

to the resynchronization stages.

Synchronous mode

In synchronous mode we can configure both the CPU and the external DDR memory to run

at 333 MHz. In this case, the SYS_CLK provides the clock to all the internal blocks (CPU

and system bus) and to the DDR external memory.

Asynchronous mode

We can configure the CPU to run at 333 MHz and the HCLK bus to run at 166 MHz, but

have the external DDR memory running at 266 MHz to reduce the board cost. In this

example, PLL1 provides the clock to all the internal blocks (CPU and system bus) while

PLL2 provides the frequency to the external memory.

Table 119.

System source control selection

Mode

rtc_disable

bit

System clock source (output of M2 multiplexer (see

Figure 110

on page 331)

NORMAL

PLL1

SLOW

24 MHz oscillator clock divided by 2, 4, 16 or 32

DOZE

CLK32KHz

DOZE

24 MHz oscillator clock divided by 2, 4, 16 or 32

SLEEP

CLK32KHz

SLEEP

24 MHz oscillator clock divided by 2, 4, 16 or 32

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