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RM0319 数据表(PDF) 338 Page - STMicroelectronics |
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RM0319 数据表(HTML) 338 Page - STMicroelectronics |
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338 / 368 page ![]() Power, reset and clock control RM0319 338/368 Doc ID 022640 Rev 3 Since the output clock is high for one input clock cycle, the duty cycle is: 100 (%) ⋅ ⎟ ⎠ ⎞ ⎜ ⎝ ⎛ = Y X DC If the post divider by two is enabled, the DC is 50%; in this case the output frequency is given by the Fout formula above. It can be shown that the period drift in this case is twice the input clock period. |
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