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PM0223 数据表(PDF) 103 Page - STMicroelectronics |
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PM0223 数据表(HTML) 103 Page - STMicroelectronics |
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103 / 110 page  DocID025763 Rev 1 103/110 PM0223 STM32L0 Core Peripherals 108 If the region size is 32B, the ADDR field is bits [31:5] and there is no Reserved field. The ADDR field The ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZE field in the MPU_RASR, defines the value of N: N = Log2(Region size in bytes), If the region size is configured to 4GB, in the MPU_RASR, there is no valid ADDR field. In this case, the region occupies the complete memory map, and the base address is 0x00000000 . The base address must be aligned to the size of the region. For example, a 64KB region must be aligned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000. 4.5.5 MPU Region Attribute and Size Register The MPU_RASR defines the region size and memory attributes of the MPU region specified by the MPU_RNR, and enables that region and any subregions. See the register summary in Table 34 on page 99 for its attributes. The bit assignments are: Bits N-1:5 Reserved, forced by hardware to 0. Bit 4 VALID: MPU region number valid Write: 0: MPU_RNR register not changed, and the processor: – Updates the base address for the region specified in the MPU_RNR – Ignores the value of the REGION field 1: the processor: – updates the value of the MPU_RNR to the value of the REGION field – updates the base address for the region specified in the REGION field. Read: Always read as zero. Bits 3:0 REGION[3:0]: MPU region field For the behavior on writes, see the description of the VALID field. On reads, returns the current region number, as specified by the MPU_RNR register. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved XN Reserv ed AP[2:0] Reserved S C B rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SRD[7:0] Reserved SIZE EN ABLE rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:29 Reserved Bit 28 XN: Instruction access disable bit: 0 = Instruction fetches enabled. 1 = Instruction fetches disabled. Bit 27 Reserved, forced by hardware to 0. |
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