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PM0223 数据表(PDF) 105 Page - STMicroelectronics |
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PM0223 数据表(HTML) 105 Page - STMicroelectronics |
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105 / 110 page  DocID025763 Rev 1 105/110 PM0223 STM32L0 Core Peripherals 108 Table 37 shows the encodings for the C, B, and S access permission bits . Table 38 shows the AP encodings that define the access permissions for privileged and unprivileged software . 4.5.7 MPU mismatch When an access violates the MPU permissions, the processor generates a HardFault. 4.5.8 Updating an MPU region To update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR and MPU_RASR registers. Updating an MPU region Simple code to configure one region: ; R1 = region number ; R2 = size/enable ; R3 = attributes ; R4 = address LDR R0,=MPU_RNR ; 0xE000ED98, MPU region number register Table 37. C, B, and S encoding C B S Memory type Shareability Other attributes 0 0 -(1) 1. The MPU ignores the value of this bit. Strongly-ordered Shareable - 1 -(1) Device Shareable - 1 0 0 Normal Not shareable Outer and inner write-through. No write allocate. 1 Shareable 1 0 Normal Not shareable Outer and inner write-back. No write allocate. 1 Shareable Table 38. AP encoding AP[2:0] Privileged permissions Unprivileged permissions Description 000 No access No access All accesses generate a permission fault. 001 RW No access Access from privileged software only. 010 RW RO Writes by unprivileged software generate a permission fault. 011 RW RW Full access. 100 Unpredictable Unpredictable Reserved. 101 RO No access Reads by privileged software only. 110 RO RO Read only, by privileged or unprivileged software. 111 RO RO Read only, by privileged or unprivileged software. |
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